天津滨海新区集成电路设计服务中心设计培训通知

IC Compiler HDP & CTS培训通知
天津滨海集成电路设计服务中心将于2012年11月22日-23日举办Synopsys公司设计软件“IC Compiler CTS & HDP”培训课程，以帮助IC工程师进一步全面系统地理解IC设计概念与方法和EDA工具的应用。培训将采用Synopsys公司相关领域的培训教材，并由Synopsys公司资深工程师主讲，培训方式以讲课和实验穿插进行。 
IC Compiler 2: HDP & CTS 
Overview
The workshop teaches floorplan preparation for large and complex integrated circuits. You will learn to partition a design into hierarchical sub-blocks for implementation in IC Compiler. All the floorplan, constraint, and timing information required for implementation is created.
We begin with an initialized floorplan (learned in the IC Compiler 1 workshop). Next, standard cell and macro placement, using plan groups, guide the development of a physical hierarchy. Manipulation of the physical hierarchy is discussed in detail.
We then demonstrate a number of methods for improving the quality of the floorplan including: power network synthesis, in-place optimization, and budgeting. Finally, we create soft macro blocks suitable for place and route processing.
Hands-on labs for all course units use a hierarchical design allowing exploration of all aspects of virtual flat floorplanning.
In this workshop, you learn how to explore the clock tree structure through various reporting commands and how to use the CTS GUI to analyze and verify settings. The workshop goes in-depth into clock tree synthesis methodology and flows for typical 90nm and 65nm designs. You also learn how to use the log to understand the tool messages that are critical to analyzing and debugging CTS results. Reducing clock tree power and avoiding hot spots by careful clock buffer placement is covered. Finally, the basics of MCMM processing of clock trees is considered.
The workshop is accompanied by comprehensive hands-on labs, which provide an opportunity to apply key concepts covered during the lectures.
Objectives 
At the end of this workshop the student should be able to:
l  Describe the IC Compiler Design Planning Virtual Flat Placement flow
l  Manipulate the hierarchy and create plan groups using the Hierarchy Browser
l  Perform Power Planning using IC Compiler's Power Network analysis and synthesis capabilities
l  Describe the IC Compiler Design Planning Virtual Flat Placement flow
l  Manipulate the hierarchy and create plan groups using the Hierarchy Browser
l  Perform power planning using IC Compiler's power network analysis and synthesis capabilities
l  Execute virtual flat placement and refine the plan groups
l  Perform in-place optimization
l  Perform plan-group-aware routing (PGAR) pin assignment on all blocks
l  Perform design budgeting and generate block-level SDC files
l  Generate ILM models for chip-level timing analysis and budgeting
l  Define and develop effective time budgeting for place & route in IC Compiler
l  Analyze the clock tree structure prior to running CTS
l  Check for valid clock definitions
l  Use the clock options correctly
l  Identify good vs. bad buffers/inverters for CTS
l  Specify different buffers/inverters for specific optimizations within CTS
l  Use Non-Default Routing rules (NDR) appropriately
l  Describe how to perform clock shielding, how to run low power CTS Flow and use the IC Compiler CTS flows
l  Perform clock tree synthesis in debug mode to obtain additional tool messages
l  Debug QoR problems
l  Optimize clock power before CTS and combat thermal hot-spots by controlling clock cell spacing
l  Use the interactive CTS browser to analyze and debug clock structures before and after synthesis
l  Use MultiCorner MultiMode technology with the synthesis of the clock trees
Course Outline 
Day 1
Introduction & Overview
Partition Top Level into Plan Groups
Create Block Macros and Integrate Top
Course Outline
Day 2
Pre-CTS Check and Setup
Building Clock Trees
Debugging and Refining Clock Trees

培训日期：2012年11月22日-2012年11月23日(食宿自理)
上课时间：上午9：30-12：00  下午1：00-4：30
名额限制：16人
地点：天津开发区第四大街80号天大科技园A1座2楼
联系人：赵先生
电话：59856076
传真：（+8622）59856068
E-mail：zhaozh@innovateda.org

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