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天津瑞发科半导体技术有限公司较新招聘信息

天津瑞发科半导体技术有限公司较新招聘信息

  • 分类:企业招聘
  • 作者:
  • 来源:
  • 发布时间:2010-10-15 18:36
  • 访问量:

【概要描述】

天津瑞发科半导体技术有限公司较新招聘信息

【概要描述】

  • 分类:企业招聘
  • 作者:
  • 来源:
  • 发布时间:2010-10-15 18:36
  • 访问量:
详情

  天津瑞发科半导体技术有限公司位于天津华苑高新区,由多名归国硅谷半导体技术专家创立,专注基于高速模拟电路技术的消费电子SOC的设计开发和销售,产品主要应用于移动存储、安防监控产品等市场。公司成立至今,在去年严重全球经济危机和半导体市场大衰退的背景下,凭借创业团队拥有的世界先进技术和对中国消费电子市场从标清到高清,从低速到高速的升级换代趋势的精准掌握,成功融得重要产业风险投资资金,并经过研发团队卓有成效的工作,在*款SOC的产品开发方面进展顺利。公司比照北京标准提供有竞争力的薪资福利待遇,员工分红及期权激励机制,拥有广阔的发展空间,我们期待您的加盟!

Company HR email: jing.shi@norelsys.com

 

 1. Digital ASIC Design Engineer (Senior and entry levels) (数字IC设计工程师)

 

Functions:

 

  Develop micro-architecture based on specification and customer input.

 

Develop implementation spec for sub-blocks.

 

 Verilog design, DFT and timing closure.

 

 Block level verification and FPGA prototyping.

 

Requirements:

 

  Solid knowledge of semiconductor logic design and flow, familiar with Synthesis and Static Timing Analysis.

 

   Strong programming skills (C/C++/SystemC/Verilog).

 

   Familiar with UNIX environment Perl/ TCL/bash/csh.

 

  Strong analytical and problem solving capability.

 

   Good communication skills and presentation skills, easy to work with.

 

  Detail oriented, methodical.

 

  Able to read and interpret English specifications and documents accurately.

 

   BS, MS or Ph.D. degree in Computer Science or Electrical Engineering.

 

 

 

2. Digital ASIC Verification Engineer (Senior and entry levels) (数字IC验证工程师)

 

Functions:

 

  Develop the infrastructure and test-bench for the validation of RTL design.

 

  Develop directed and random tests.

 

  RTL simulation and hardware emulation.

 

  Lead the process/methodology development and execution.

 

Requirements:

 

  Solid knowledge of semiconductor logic design and flow.

 

 Strong programming skills (C/C++/SystemC/Verilog).

 

 Fluent in UNIX script programming (Perl/ TCL/bash/csh).

 

 Have developed verification environment(s) and test cases.

 

  Extensive RTL development experience (Verilog or VHDL) is a plus.

 

  Good communication skills and presentation skills, easy to work with.

 

 Detail oriented, methodical.

 

  Fluent in English. Able to read, write and interpret English specifications and documents accurately.

 

 BS, MS or Ph.D. degree in Computer Science or Electrical Engineering.

 

 

 

3. Firmware Engineer (Embedded software、嵌入式软件工程师)

 

Functions:

 

  Develop 8051 firmware for new products.

 

Requirements

 

  Familiar with PC hardware as well as embedded systems.

 

 Solid background in C and C++.

 

  Experienced in 8051 assembly and firmware development.

 

  BS, MS or Ph.D. degree in Computer Science or Electrical Engineering.

 

 

 

4. Software Engineer (软件工程师)

 

Functions:

 

 Develop USB drivers for Microsoft Windows OS (XP, Vista, Windows 7).

 

  Develop and maintain GUI software on PC for hardware debugging board and OEM customization tool.

 

   Work with hardware development team to bring up and debug new products.

 

    Customize software to suit OEM’s need.

 

Requirements

 

  Familiar with PC hardware, Microsoft Windows OS (XP, Vista, Windows 7) as well as embedded systems.

 

  Solid background in C and C++.

 

  Extensive experience with user interface development using Win32 API.

 

  Familiar with USB driver development on Windows OS (XP, Vista, Windows 7).

 

  MS in CS or EE, or BS plus 4 years of related experience.

 

 

 

5.  Senior Analog and Mixed-signal Design Engineer (级别高模拟IC、混合电路设计工程师)

 

Functions:

 

   Analysis, design, and characterization of high speed (1-6Gb/s) analog and mixed-signal integrated circuits for wireline applications, such as PLL, VCOs, high speed I/O, equalizer, SERDES, CDR, etc.

 

  Work on block level mixed signal integration and verifications.

 

   Supervise layout of analog circuits.

 

   Must be strong individual contributor and also able to work as member of a small team.

 

 

 

Requirements:

 

  Industry experience in design of analog and mixed-signal blocks, and advanced design skills in some of the following areas:

 

(a). PLL/DLL, regulators, VCOs, etc.

 

(b). high speed (multi-Gbps) interfaces, wireline driver, receiver, equalizer, etc.

 

(c). high speed SERDES, CDR.

 

  Extensive experience with design and layout tools such as Cadence Virtuoso, Cadence Spectre-RF, HSPICE, or other similar simulators and layout tools.

 

   Good understanding of semiconductor devices and technology.

 

  Experience in IC design verification and testing.

 

 Experience in testing and characterization of high speed ICs is a plus.

 

 Knowledge of Matlab/Verilog modeling of analog circuits such as PLL and CDR is a plus.

 

  M.S. degree with 5+ years of experience or PhD with 3+ years of experience in analog and mixed-signal IC design using CMOS technology.

 

 

 

6. Analog and Mixed-signal Design Engineer (模拟IC、混合电路设计工程师)

 

Functions:

 

  Analysis, design of high speed (1-6Gb/s) analog and mixed-signal integrated circuits for wireline applications, such as PLL, VCOs, high speed I/O, equalizer, SERDES, CDR, etc.

 

  Custom design of high speed CMOS digital circuits.

 

   Supervise layout of analog circuits and high-speed digital circuits.

 

   Self-motivated and also able to work as member of a small team.

 

 

 

Requirements:

 

  Experience and good understanding of analog and mixed-signal blocks, including some of the following areas:

 

(a). PLL/DLL, regulators, VCOs, etc.

 

(b). high speed (multi-Gbps) interfaces, wireline driver, receiver, equalizer, etc.

 

(c). high speed SERDES, CDR.

 

  Experience with design and layout tools such as Cadence Virtuoso, Cadence Spectre-RF, HSPICE, or other similar simulators and layout tools.

 

  Good understanding of semiconductor devices and technology.

 

   M.S. degree with 2+ years of experience or PhD degree in analog and mixed-signal IC background.

 

 

 

7. Physical Layout Engineer (IC版图设计工程师)

 

Functions:

 

  Analog and Mixed signal IC custom layout design.

 

  Chip/Top level floorplanning and integration (Senior layout engineer).

 

 

 

Requirements:

 

  Familiar with Cadence design environment (Virtuoso) and Verification such as Mentor Calibre.

 

  Industry experience in layout of analog and mixed-signal ICs, such as high speed (GHz) analog circuits including PLLs and high-speed I/Os, etc.

 

   Good understanding of design rules, device matching, and isolation techniques.

 

   Basic understanding of semiconductor devices and IC process manufacturing.

 

   Experience in top level floorplanning and integration is a plus.

 

   B.S. degree in EE or Microelectronics with 3+ years of IC layout experience.

 

 

 

天津瑞发科半导体技术有限公司

 

地址:天津华苑产业区华天道8号海泰信息广场B-1108

电话:83715190

手机:15222785076

 

邮箱:jing.shi@norelsys.com

客服热线
022-83945506 022-83945506
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