JD for ASIC design manager
- Manage the development of complex ASIC chips
- Management, technical leadership and mentoring skills
- Experienced in the ASIC design flow, DFT, timing analysis, floor planning, ECO flow, STA, Silicon bring up flow
- Experience in flat and hierarchical top-down P&R flows
- Experience in logic design, synthesis, functional & timing verification skills
- Familiar with Perl or TCL
- Proven tape-out experience
- 6+ years relevant work experience
- M.S. or Ph.D. in Electrical Engineering or Computer Science.
JD for SI engineer
Signal Integrity Engineer
- Responsible for signal integrity design and characterization of GHz high-speed serial link channel.
- Perform signal integrity design and characterization of chip and board design.
- The job includes but not limits to: signal integrity & power integrity analysis, package design and BER (Bit Error Rate) test.
- Familiar with Spice, ADS, HFSS and so on
- Knowledge of signal integrity and power integrity
- Familiar with high speed serial link technologies is a plus
- M.S. or Ph.D. in Electrical Engineering or equivalent, Ph.D. is preferred.
- Background in RF or Microwave is a plus.