(二)EDA基础工具培训课程:
Synopsys公司课程:
□ Assertion Based Verification (SVA)
□ Astro 1
□ Astro-Rail: Full-Chip Reliability Analysis
□ Design Compiler 1
□ Design Compiler Essentials for Place and Route
□ DFT Compiler 1
□ Encore Basics
□ Formality
□ Hercules Beginning Runset Development
□ Hercules Beginning Users
□ HSPICE Essentials (2days)
□ HSPICE Advanced Topics (2days)
□ IC Compiler 1
□ ICC-PC
□ JupiterXT 1
□ Library Development (2days)
□ MAST Modeling
□ Nanosim
□ Nanosim Advanced
□ Pathmill Timing Characterization
□ Pathmill Timing Verification
□ Physical Compiler 1
□ Power Compiler
□ PrimeRail
□ PrimeTime 1
□ PrimeTime SI: Crosstalk Delay and Noise
□ PrimeTime: Debugging Constraints
□ Saber Designer Mixed-Signal & Mixed-Technology Simulation
□ Star-RCXT
□ TetraMAX 1
□ VERA I
□ OpenVera Reference Verification Methodology (RVM)(2days)
□ Verification with VCS-MX
Cadence公司课程:
□ Incisive Simulation – v6.1 (2days)
□ Specman Elite Basics for verification Envionment Users(2days)
□ Logic Equivalence Checking with Encounter Conformal - v7.1 (1days)
□ Low-Power Implementation 6_2 (2 days)
□ Signoff_Timing_and_SI_Analysis_with_Encounter_Timing_System V7.1 (2 day)
□ Encounter_RTL_Compiler v7.1 (2 days)
□ SoC Encounter XL RTL to GDSII Hierarchical Flow- v6.1 (2days)
□ Physical Implement with SoC Encounter XL - v7.1(2days)
□ Virtuoso Layout Editor - v5.1.41(2days)
□ Assura Verification - v3.1.4(3days)
□ The advanced design flow for nanometer analog applications(2days)
□ Virtuoso Analog Design Environment (3days)
□ Allegro Design Entry HDL Front-to-Back Flow(3days)
□ Allegro PCB Editor - v15.7
□ Allegro PCB SI Foundations - v15.7
□ Package Design with APD(Allegro Package Designer)(3days)
培 训 申 请 表
参加课程名称: |
|
企/事业单位名称: |
|
企/事业单位地址: |
|
参加培训人数: |
|
参见培训人员姓名: |
|
联系人姓名: |
|
电话: |
|
传真: |
|
E-mail: |
|
备注: |
|
注:
- 请认真填写上述信息;
- 关于培训费用将以上述参加培训人数为计算基数,且一旦确认将不得更改,因此所造成的经济损失本中心概不负责;
- 请将申请表格加盖单位公章后,以传真或邮寄方式返回本中心,如以传真形式则在人员报到时出示原件;
- 本中心享有最终解释权