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（二）EDA基础工具培训课程：
Synopsys公司课程：
□ Assertion Based Verification (SVA)
□ Astro 1
□ Astro-Rail: Full-Chip Reliability Analysis
□ Design Compiler 1
□ Design Compiler Essentials for Place and Route
□ DFT Compiler 1
□ Encore Basics
□ Formality
□ Hercules Beginning Runset Development
□ Hercules Beginning Users
□ HSPICE Essentials (2days)
□ HSPICE Advanced Topics (2days)
□ IC Compiler 1
□ ICC-PC
□ JupiterXT 1
□ Library Development (2days)
□ MAST Modeling
□ Nanosim
□ Nanosim Advanced
□ Pathmill Timing Characterization
□ Pathmill Timing Verification
□ Physical Compiler 1
□ Power Compiler
□ PrimeRail
□ PrimeTime 1
□ PrimeTime SI: Crosstalk Delay and Noise
□ PrimeTime: Debugging Constraints
□ Saber Designer Mixed-Signal & Mixed-Technology Simulation
□ Star-RCXT
□ TetraMAX 1
□ VERA I
□ OpenVera Reference Verification Methodology (RVM)(2days)
□ Verification with VCS-MX
Cadence公司课程：
□ Incisive Simulation – v6.1 （2days）
□ Specman Elite Basics for verification Envionment Users(2days)
□ Logic Equivalence Checking with Encounter Conformal - v7.1 (1days)
□ Low-Power Implementation 6_2 (2 days)
□ Signoff_Timing_and_SI_Analysis_with_Encounter_Timing_System V7.1 (2 day)
□ Encounter_RTL_Compiler v7.1 (2 days)
□ SoC Encounter XL RTL to GDSII Hierarchical Flow- v6.1 (2days)
□ Physical Implement with SoC Encounter XL - v7.1(2days)
□ Virtuoso Layout Editor - v5.1.41(2days)
□ Assura Verification - v3.1.4(3days)
□ The advanced design flow for nanometer analog applications(2days)
□ Virtuoso Analog Design Environment (3days)
□ Allegro Design Entry HDL Front-to-Back Flow(3days)
□ Allegro PCB Editor - v15.7
□ Allegro PCB SI Foundations - v15.7
□ Package Design with APD(Allegro Package Designer)(3days)
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